Network synchronization environment

Overview

Careful consideration should be given to proper design of the SONET network's synchronization environment. Proper synchronization engineering minimizes timing instabilities, maintains quality transmission network performance, and limits network degradation due to unwanted propagation of synchronization network faults. The synchronization features of the Alcatel-Lucent 1665 DMX are designed to complement the existing and future synchronization network and allow it not only to make use of network timing but also to take on an active role in facilitating network synchronization.

Published sources

A number of published sources give generic recommendations on setting up a synchronization network. Alcatel-Lucent 1665 DMX is designed to operate in a network that complies with recommendations stated in GR-253-CORE and the following documents:

• GR-436-CORE, Digital Synchronization Network Plan

• GR-378-CORE, Generic Requirements for Timing Signal Generators (TSG)

• ANSI T1.101, Synchronization Interface Standards for Digital Networks

• GR-1244-CORE, Clocks for the Synchronized Network: Common Generic Criteria.

Recommendations

The following are some key recommendations from the documents listed above. For further detailed explanation, the sources should be consulted directly.

1. A node can only receive the synchronization reference signal from another node that contains a clock of equivalent or superior quality (Stratum level).

2. The facilities with the greatest availability (absence of outages) should be selected for synchronization facilities.

3. Where possible, all primary and secondary synchronization facilities should be diverse, and synchronization facilities with the same cable should be minimized.

4. The total number of nodes in series from the Stratum 1 source should be minimized. For example, the primary synchronization network would ideally look like a star configuration with the Stratum 1 source at the center. The nodes connected to the star would branch out in decreasing Stratum level from the center.

5. No timing loops may be formed in any combination of primary and secondary facilities.

Stratum 3 timing generator

Alcatel-Lucent 1665 DMX supports a Stratum 3 Timing Generator (TG3) embedded in each high speed (MAIN) Main Switch pack (LNW80), OC-12, OC-48, and OC-192 optical interface circuit pack. The TG3 operates with an internal oscillator of ±4.6 ppm long-term accuracy in the free running mode, while in holdover the accuracy is ±.37 ppm over the full −40ºC to +65ºC temperature range. The TG3 should be used according to the recommendations in the documents referenced previously.