Use this procedure to provision system timing for circuit packs.

The following system timing modes are supported.

• External Timing (VLNC6x circuit packs only): The BITS (Building Integrated Timing Supply) option specifies that the System clock is derived from an external reference signal traceable to a common Primary Reference Clock in the network. The shelf has a DS1/E1 input interface associated with each main slot for receiving the external timing reference signal.

  When BITS is selected for VLNC64 circuit packs, an optional alternate source of timing, Line, can be specified. In Line timing, the VLNC64 circuit pack derives timing from the incoming OC3/STM1 interface.

• 1588ver2 Precision Timing Protocol Timing (VLNC6x circuit packs only): The ptp-1588 option specifies that IEEE 1588 version 2 protocol is used to drive the system timing. This is useful for remote locations where no high-quality reference clock signal is available.

• Free Running Timing: The free-running option specifies that the System clock is derived from a local oscillator.

  This option is recommended for use when all DS1/E1 interfaces on VLNC60/61 circuit packs offer MLPPP service.

  The free-running option is also supported on VLNC42/42B circuit packs.

• SONET/SDH Line Timing (VLNC64 circuit pack only): The line option specifies that the System clock is derived from an OC-3/STM-1 line on the VLNC64 circuit pack.

• SyncE Line Timing: The ge option specifies that the System clock is derived from an SFP-based Gigabit Ethernet interface.

  When ge is selected on the VLNC42/42B circuit packs, the GE interface derived signal is sent to the adjacent VLNC6x/VLNC52/55 circuit pack via the backplane. The VLNC42/42B circuit pack System clock is derived from the incoming 25 Mhz clock from the adjacent VLNC6x/VLNC52/55 circuit pack.

• Backplane Timing: The backplane option specifies that the System clock is derived from the backplane 25 MHz reference. Timing is derived from the adjacent circuit pack.

Differential timestamp frequency

The differential timestamp frequency of VLNC6x circuit packs may be provisioned as 25 MHz or 77.76 MHz (default).

The system at the other endpoint of the Circuit Emulation Service must be provisioned with the same differential timestamp frequency value.

This command causes the system to reset. The differential timestamp frequency cannot be cleared using the clear config command. This procedure must be performed to modify the provisioned value.

The Series 1:2 or later VLNC64 circuit pack is required to support 25 MHz frequency.