Synchronization is an important part of all SONET/SDH products. Alcatel-Lucent 1850 TSS-5, equipped with a VLNC2 and VLNC50/52/55, VLNC42, and VLNC6x circuit packs is designed for high performance and reliable synchronization and can be used in a number of synchronization environments.
VLNC50/52/55 circuit pack timing is provided by an internal SONET Minimum Clock (SMC) Timing Generator (no synchronization inputs), or SDH Equipment Clock, Option 2 (SEC). Internal timing functions such as reference interfaces, the on-board clock elements, and timing distribution, are provided by the SMC/SEC Timing Generator. The timing generator distributes clock and frame signals, derived from the ±20 ppm generator, to any companion VLNC50/52/55, VLNC35, or VLNC4x circuit pack.
The VLNC52/55 circuit pack supports synchronous Ethernet by transmitting timing and Ethernet synchronization status messages on the Gigabit Ethernet interface. The VLNC52/55 circuit pack also provides a 25 MHz backplane reference signal for VLNC4x circuit packs. The VLNC52 circuit pack cannot recover timing reference signals or Ethernet synchronization status messages from the Gigabit Ethernet interface. Beginning in Release 7.2.2, the VLNC55 circuit pack can recover timing reference signals or Ethernet synchronization status messages from the Gigabit Ethernet interface. Refer to the Backplane bullet in Synchronization features on the VLNC50/52/55 circuit packs.
VLNC42/42B circuit pack timing is provided by an internal SONET Minimum Clock (SMC) Timing Generator and clock extraction from any Gigabit Ethernet interface. Internal timing functions such as reference interfaces, the on-board clock elements, and timing distribution, are provided by the SMC/SEC Timing Generator. The timing generator transmits timing, derived from the ±20 ppm generator, and Ethernet synchronization status messages to any synchronous Ethernet port. The VLNC42/42B circuit pack can recover Ethernet synchronization status messages from any synchronous Ethernet port. Beginning in Release 7.2.2, the VLNC42B can also recover sync status messages from the VLNC55 via the backplane port. Refer to the Backplane bullet in Synchronization features on the VLNC50/52/55 circuit packs.
VLNC6x circuit pack timing is provided by an internal Stratum 3 Timing Generator and clock extraction from any Gigabit Ethernet interface, optical line, or BITS clock. Internal timing functions such as reference interfaces, the on-board clock elements, and timing distribution, are provided by the Stratum 3 Timing Generator. The timing generator transmits timing, derived from the ±4.6 ppm generator, and Ethernet synchronization status messages to any synchronous Ethernet port. The VLNC6x circuit pack can also recover Ethernet synchronization status messages from any synchronous Ethernet port.
Alcatel-Lucent 1850 TSS-5 VLNC60, VLNC61, VLNC62, and VLNC64 circuit packs support the following synchronization modes:
System Timing provides the timing information for all devices on the VLNC60, VLNC61, VLNC62, or VLNC64 pack. The sources for this timing are:
Building Integrated Timing Supply, BITS
BITS is a timing source traceable to a common Primary Reference Clock in the network. The shelf has a special DS1/E1 input interface associated with each main slot for receiving this timing.
Line (applicable only to the VLNC64)
In this mode, the System Timing is derived from an OC-3/STM-1 line on the VLNC64 pack.
Precision Timing Protocol, 1588v2
The VLNC60/VLNC61/VLNC62/VLNC64 packs can be deployed in remote locations where there is no access to physical external clocking source, such as BITS. In such cases, timing information is distributed across the network using a Precision Timing Protocol known as 1588. VLNC60/VLNC61/VLNC62/VLNC64 implement version 2 of the protocol (1588v2). This protocol may be run in Master mode or Slave mode. The pack which has access to external timing source is run in Master mode.
The pack running in 1588 Master mode distributes the clocking information across a network over Ethernet. At remote locations, 1588 must run in Slave mode. In Slave mode, the pack derives System Timing from 1588 protocol messages being received from the Master system in the network.
Free running
The VLNC60/VLNC61/VLNC62/VLNC64 circuit pack contains a Stratum 3 (ST3/SEC) oscillator (±4.6 ppm). In Free Running mode, this oscillator serves as the timing source for the pack. Free running is the default System Timing mode. When all the interfaces on the pack provide ML-PPP service, free running is the recommended mode. In all other situations, one of the other system timing modes should be provisioned.
Holdover
When the pack loses a valid timing input, the timing generator switches to holdover mode and continues to provide system timing, using the internal oscillator to maintain the last known good reference frequency.
Interface timing refers to the timing source of the DS1/E1, OC-3/STM-1 interfaces on the VLNC60, VLNC61, VLNC62, and VLNC64 circuit packs.
System
In this mode, the interface derives its timing from the same source as the System Timing. System is the default timing mode for the individual interfaces.
Loop
In this mode, the interface derives its timing from the incoming signal of the interface.
Differential
In this mode, the interface derives its timing by taking into account the System Timing and information it retrieves from the Real Time Protocol (RTP) timestamps of the Pseudowire. These RTP timestamps are sent by the VLNC60/VLNC61/VLNC62/VLNC64 packs on the pseudowire as part of the RFC 4553 header.
Differential timing is required on DS1/E1 interfaces carrying Circuit Emulation traffic.
Differential Timing Domain
The VLNC64 pack has internal resources to generate and recover RTP differential timestamps. These timestamps are carried in the SAToP (RFC 4553) encapsulated data traffic. The information contained in this timestamp is used to recover timing information from the embedded TDM signal in the data frame, when it reaches the other end of the packet network.
On the VLNC64 there are up to 28 internal resources which can generate/recover the RTP differential timestamps. This means that up to 28 TDM timing domains can be generated/recovered from these data frames. The VLNC64 supports up to 84 DS1 or 63 E1 signals. Since there can be only 28 distinct TDM timing domains, these DS1/E1 signals must be grouped into 28 timing domains. In each group, one of the DS1/E1 signals serve as the source of timing for all other DS1/E1 signals in the group. The DS1/E1 signals on VLNC64 that are used to carry the TDM traffic must be grouped into one of these domains.
Although differential timestamps are applicable to the VLNC60/61/62 pack, the number of timing domains is greater than the number of DS1/E1 interfaces on it. The system internally manages the domain value allocation. Therefore, you cannot explicitly configure this parameter on VLNC60/61/62.
Alcatel-Lucent 1850 TSS-5 supports three synchronization modes. These timing modes are supported by the embedded internal SONET Minimum Clock (SMC) Timing Generator (no synchronization inputs) or SDH Equipment Clock, Option 2 (SEC) in the VLNC50/52/55 circuit packs. The basic timing modes can be combined into various network configurations.
Line timing
Line timing is derived from incoming OC-3/OC-12/OC-48 or STM-1/STM-4/STM-16 signal (for small COs or remote sites). In line timing mode, the timing generator derives local shelf timing from the incoming OC-n/STM-n signal to the VLNC50/52/55. If the incoming reference is corrupted, unavailable, or lost (for example, due to a cable cut), the timing generator will switch to holdover mode. The timing generator will normally switch back to the line timing mode when a good reference is available, but it can be provisioned to require a manual switch.
In line timing mode the VLNC50/52/55 can also provide DS1/E1 sync output, derived from the incoming line.
Backplane (applicable only with a VLNC55 in main-1 and a VLNC42 or VLNC42B in main-2 (rtrv-eqpt:main-2:APP=VLNC42 or VLNC42B)
In this mode, the VLNC55 can derive timing from the backplane (when the adjacent pack is a VLNC42/42B). SyncE timing is passed from the VLNC42/42B to the VLNV55. Timing recovered from the backplane is used to time all SyncE outgoing GE/FE signals on the VLNC42/42B. Timing recovered from the backplane is also used to time the SONET/SDH and GbE interfaces of the VLNC55.
Free running
In free running from the internal SMC or SEC, mode switching is not performed. The timing generator derives timing from the internal timing generator in the VLNC50/52/55. The SMC/SEC oscillator provides ±20 ppm accuracy. At most, one NE in a network should be provisioned in the free running mode. All other NEs in the subnetwork should be line timed to this free running system to avoid performance degradation.
Holdover
When there is a synchronization reference failure on a system that is line timed and unprotected, a timing generator switches to holdover mode and continues to provide system timing, using the internal oscillator to maintain the last known good reference frequency.
Alcatel-Lucent 1850 TSS-5 also supports a DS1 (OC-n) or an E1 (STM-n) timing output feature that facilitates network timing distribution. DS1 (OC-n) and E1 (STM-n) timing outputs are available with the VLNC50/52/55. The DS1/E1 timing output is derived from the OC-n/STM-n line rate, so it is not subjected to multiplexing or pointer processing effects. The result is a DS1/E1 traceable to the far-end source with extremely low jitter and wander. The timing output can be locked to an OC-n/STM-n line or the OC-n/STM-n source can be automatically selected using synchronization messages. In either case Threshold AIS may be enabled to insert AIS if the synchronization message of the OC-n/STM-n source matches a provisioned threshold.
The frame format on the DS1 output is provisionable as superframe format (SF) or extended SF (ESF). The E1 frame format can be provisioned as FAS or CRC4. The DS1/E1 is a framed all-ones signal under normal conditions or an AIS signal under failure conditions.
When the system interface standard parameter is provisioned to SDH, the External synchronization output - source and Wait-to-Restore parameters are provisionable. The external synchronization output, if enabled, may be derived from the line timing reference or the system clock. TheWait-to-Restore interval specifies the time (in minutes) that the reference must remain good before being considered as an available timing reference.
The Alcatel-Lucent 1850 TSS-5 shelf provides physical connections for timing inputs and outputs. Currently, the physical timing connections are multi-wire connections. Beginning in Release 6.0, Alcatel-Lucent 1850 TSS-5 supports a 75 ohm BNC interface for E1 timing. The interface converter provides the physical and impedance transformation to accommodate a 75 ohm E1 interface for both input and output timing signals. In most cases, a single shelf would contain either an input timing converter or an output timing converter, not both.
Alcatel-Lucent 1850 TSS-5 accepts two twisted pair timing inputs: one for each main slot - Main1 [M1] and Main 2 [M2]. The twisted pair interface is three-wire 100 ohm or 120 ohm with tip, ring, and ground. The physical receptacle is a spring-loaded terminal block on the VLIU. The interface converter allows a 75 ohm BNC cable to connect E1 timing signals to the shelf. The VLNC50/52/55 and VLNC60, VLNC61, VLNC62, and VLNC64 circuit packs support the E1 timing input converter.
Alcatel-Lucent 1850 TSS-5 shelf supports a synchronization output signal. The Sync Out interface is a three-wire 100 or 120 ohm with tip, ring, and ground. The physical connection for VLNC6x packs is an RJ-45 connector on the VLIU. The physical connection for VLNC5x packs is a three-wire tip/ring/ground on the terminal block on the VLIU. The E1 interface converter provides a 75 ohm BNC connection for the output synchronization signal from an RJ-45 connector on the VLIU. The E1 timing output interface from the RJ45 connection is only supported by the VLNC62 circuit pack.
The Alcatel-Lucent 1850 TSS-5 supports synchronous Ethernet on Fast Ethernet and Gigabit Ethernet interfaces. A synchronous Ethernet architecture requires a primary reference clock feeding a network element in an Ethernet network. The primary reference clock for Synchronous Ethernet could be located in different parts of the network.
When the physical layer transmitter clock is derived from a high quality reference clock, the receivers lock on the physical layer clock of the received signal and gain access to a stable and accurate frequency reference. The port transmitter clock is also locked to the accurate reference frequency. Synchronous Ethernet standardization as a network-wide solution is described in ITU-T Recommendation G.8261.
Synchronization status messaging provides a mechanism for downstream Ethernet switches to determine the traceability of the synchronization distribution scheme back to the primary reference clock or highest quality clock that is available. The synchronization function processes the synchronization status messages. Under upstream network failure conditions, the synchronization function takes appropriate action based on the synchronization status messages and pre-set priorities and selects an alternate synchronization feed.
Refer to Synchronous Ethernet network configurations for details about the packs and configurations that support Synchronous Ethernet.
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