TCAM allocation on 7220 IXR-D4 and D5

The 7220 IXR-D4 and 7220 IXR-D5 have 3 groups of TCAM slices associated with 3 different stages of the forwarding pipeline.

TCAM allocation details for each stage is summarized in the following table.

Table 1. 7220 IXR-D4/D5 TCAM allocation
Stage TCAM allocation details
VFP

There are 4 VFP slices, providing a total of 4*256 = 1024 entries. All slices are allocated statically.

1 slice:

  • to strip the transport VLAN 1 tag from outbound-CPU-originated packets (to support egress mirroring of such traffic). This requires 1 entry per system.
  • to assign a virtual port (VP) to packets arriving on an untagged bridged subinterface. This requires 1 entry per untagged bridged subinterface.

3 slices for capture and system filter entries:

  • Three physical slices are grouped to support triple-wide entries.
  • One triple-wide entry is consumed by each IPv4 capture-filter entry, IPv4 system filter entry, IPv6 capture-filter entry, or IPv6 system filter entry (the system supports mapping IPv4 groups and IPv6 groups onto the same physical slices); maximum possible scale is 256 entries.
IFP

There are 12 IFP slices on 7220 IXR-D4/D5, providing a total of 12*2K = 24K entries.

On 7220 IXR-D5, all slices are allocated statically:

  • 2 slices for CPU QoS queue assignment
  • 1 slice for VXLAN ES-related functionality
  • 2 slices for ingress IPv4 ACL

    2K ingress IPv4 ACL entries are supported by group of 2 side-by-side banks (inter-slice double-wide mode). Maximum possible ingress IPv4 TCAM entries = 2048

  • 3 slices for ingress IPv6 ACL

    2K ingress IPv6 ACL entries are supported by group of 3 side-by-side banks (inter-slice triple-wide mode). Maximum possible ingress IPv6 TCAM entries = 2048

  • 2 slices for MAC ACL

    2K ingress MAC ACL entries are supported by group of 2 side-by-side banks (inter-slice double-wide mode). Maximum possible ingress MAC TCAM entries = 2048.

  • 1 slice for ingress subinterface policing

On 7220 IXR-D5, all slices are allocated statically:

  • 2 slices for CPU QoS queue assignment, providing 2048 entries
  • 1 slice for VXLAN ES related functionality, providing 2048 entries
  • 2 slices for ingress IPv4 ACLs, providing 1024 entries
  • 3 slices for ingress IPv6 ACLs, providing 1024 entries
  • 2 slices for MAC ACLs, providing 1024 entries
  • 1 slice for ingress subinterface policing, providing 2048 entries
EFP

There are 4 EFP slices providing a total of 4*512 = 2048 entries

1 slice is allocated statically. Entries serve 2 purposes:

  • ES pruning of local-biased traffic. This requires 1 entry per system.
  • Egress port mirroring statistics. This requires 1 entry per outgoing interface.
3 slices are available for dynamic allocation
  • 2 physical slices are grouped to support double-wide entries
  • 3 physical slices are grouped to support triple-wide entries
  • 1 triple-wide entry is consumed by each interface egress IPv4 filter entry, interface egress IPv6 filter entry, IPv4 CPM filter entry or IPv6 CPM filter entry (the system supports mapping IPv4 groups and IPv6 groups onto the same physical slices); maximum possible scale is 512 entries
  • 1 double-wide entry is consumed by each interface egress MAC filter entry or MAC CPM filter entry